RegViz: Visualize HPSICR Bitfield

NXP Semiconductors /MIMXRT1021 /SNVS /HPSICR

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Interpret as HPSICR

SV0_EN=DISABLED, SV4_EN=DISABLED, LPSVI_EN=DISABLED, SV3_EN=DISABLED, SV1_EN=DISABLED, SV2_EN=DISABLED, SV5_EN=DISABLED

Description

SNVS_HP Security Interrupt Control Register

Fields

SV0_EN	Security Violation 0 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 0 security violation 0 (DISABLED): Security Violation 0 Interrupt is Disabled 1 (ENABLED): Security Violation 0 Interrupt is Enabled
SV1_EN	Security Violation 1 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 1 security violation 0 (DISABLED): Security Violation 1 Interrupt is Disabled 1 (ENABLED): Security Violation 1 Interrupt is Enabled
SV2_EN	Security Violation 2 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 2 security violation 0 (DISABLED): Security Violation 2 Interrupt is Disabled 1 (ENABLED): Security Violation 2 Interrupt is Enabled
SV3_EN	Security Violation 3 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 3 security violation 0 (DISABLED): Security Violation 3 Interrupt is Disabled 1 (ENABLED): Security Violation 3 Interrupt is Enabled
SV4_EN	Security Violation 4 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 4 security violation 0 (DISABLED): Security Violation 4 Interrupt is Disabled 1 (ENABLED): Security Violation 4 Interrupt is Enabled
SV5_EN	Security Violation 5 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 5 security violation 0 (DISABLED): Security Violation 5 Interrupt is Disabled 1 (ENABLED): Security Violation 5 Interrupt is Enabled
LPSVI_EN	LP Security Violation Interrupt Enable This bit enables generating of the security interrupt to the host processor upon security violation signal from the LP section 0 (DISABLED): LP Security Violation Interrupt is Disabled 1 (ENABLED): LP Security Violation Interrupt is Enabled

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